Memory and datapath
We’ve seen the datapath and explored how the CPU executes instructions by coordinating:
- registers for temporary storage,
- the ALU for arithmetic and logic operations,
- multiplexers for data routing,
- the control unit for generating control signals, and
- the fetch-decode-execute cycle.
We’ve traced how simple instructions (ADD, LOAD, STORE, BEQ) flow through the datapath in a single-cycle datapath, where every instruction completes in one clock cycle, and how they are executed in a multi-cycle datapath, with and without pipelining.
However, we largely treated memory as a “black box”— resource that the CPU accesses for reading and writing data, with little detail.
Two types of memory access
Memory serves two distinct purposes in the CPU:
Instruction memory stores the program’s binary code.
- Instructions are read from memory during instruction fetch.
- Instruction memory is addressed using values in the program counter.
Data memory stores variables, constants, and computation results.
- Data is read or written during the execute stage (
LOADandSTOREinstructions. - Addresses in instructions may be relative to some base address with an offset, or may be absolute.
- Effective addresses are computed by the ALU.
- Data memory holds program data that changes during execution.
In the von Neumann architecture, instruction memory and data memory physically share the same, unified memory hardware. In the Harvard architecture, these two pools of memory are physically separate.
© 2025 Clayton Cafiero.
No generative AI was used in writing this material. This was written the old-fashioned way.