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A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification

TitleA Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification
Publication TypeJournal Article
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication Year2008
Publication Date07/2008
Volume27
Issue7
Pagination1343 - 1347
AuthorsZheng, H, Ahrens, J, Xia, T
ISSN0278-0070
AbstractThis paper presents a compositional method with failure-preserving abstraction for scalable asynchronous design verification. It combines efficient state-space reductions and novel interface refinement and can dramatically reduce the complexity of state space while decreasing the introduction of false failures. This allows much larger designs to be verified as demonstrated in the experimental results.
URLhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4544873
DOI10.1109/TCAD.2008.923104
Short TitleIEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
Status: 
Published
Attributable Grant: 
CSYS
Grant Year: 
Year2